The Front End Module (FEM) version 1 is an FPGA-based readout card designed and built by the Detectors and Electronics group of the Science and Technology Facilities Council. The board serves as the interface to the MedipixRX ASICs, handling control and configuration of the chips and the readout of the image data.
The FEM maintains a 1 Gb/s copper ethernet control link and a 10 Gb/s fibre optic link through which the pixel data is read out. Each FEM is connected to an individual linux server PC configured as an EPICS IOC for parallel readout of the data, enabling continuous frame rates of 250Hz whilst streaming to storage on a distributed filesystem. A burst mode is provided where the pixel data can be stored on-board the FEM in memory at a rate of 1kHz for a short time. One second of data can be stored in this mode, which can be then streamed out to storage at the end of the acquisition.
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